1. Field of the Invention
This invention relates generally to programmable logic array circuitry and more particularly, it relates to an improved dynamic PLA circuit with no "virtual grounds" for generating a faster high-to-low transition on its product term lines than has been traditionally available.
2. Description of the Prior Art
Programmable logic arrays (PLAs) are generally known as a method of implementing logic in complex digital circuits. PLAs typically have a two "plane" structure wherein there are provided two separate regions or groupings of logic gates with the outputs of one region being fed into the inputs oF the other region. For example, a basic PLA structure is comprised of a plane of AND gates reFerred to sometimes as an AND array or product term array and a plane of OR gates sometimes referred to as an OR array or sum term array. This type of two-plane PLA allows a large number of arbitrary logic operations to be implemented in an orderly manner. The orderly structure of programmable logic arrays is particularly advantageous when it comes to designing large scale integrated (LSI) circuits or very large scale (VLSI) circuits.
The logic operations implemented in the "AND" and "OR" planes of the conventional programmable logic arrays are typically performed by MOS (metal-oxide semiconductor) FETs (field-effect transistors) connected to the input lines and output lines thereof, and interconnected by means of product term lines which join the outputs of the "AND" plane MOS devices to the inputs of the "OR" plane MOS devices. A prior art arrangement of this type is shown in FIG. 1. Here, the AND plane is designated by reference numeral 1 and the OR plane is designated by reference numeral 2. The input signals IN1, IN1 . . . are set up on the input lines 3 while the AND plane is precharging (the evaluation signal AND eval/pch is at a low level). During this time, the FET MAG1 is turned off and the virtual ground on line 4 is allowed to float up via the programming FETs A1, A2, . . . whose inputs are at a high level. During the evaluation phase when the signal AND eval/pch is at a high level, the transistor MAG1 is turned on which connects the virtual ground line 4 to the ground potential.
Terms whose respective programming FETs are turned on by the input signals being at a high level will be discharged through the transistor MAG1 to the ground potential. Thus, a large discharge current, accompanied by increased power consumption, will be generated due to all of the charges on the various terms as well as the charge on the virtual ground parasitic capacitance C. It would therefore be desirable to reduce this discharge current by eliminating the virtual ground and reducing the capacitance on the term lines 6. The term line capacitance is created by the connection of the drain electrodes of the programming FETs A1, A2, . . . to the respective one of the term lines 6.
The terms which do not have a path to the ground potential will remain charged to the high level. When the OR plane 2 is being evaluated the evaluation signal OR eval/pch is at a high level), the transistor MAG2 is turned on which connects the virtual ground line 7 to the ground potential. The term lines having the high level will cause the programming FETs B1, B2, . . . in the OR plane to be turned on, thereby discharging some of the output lines B. However, the high-to-low transition on the output lines B and the virtual ground line 7 will be coupled capacitively to the term lines (now floating) having a high level. As a result, the term lines will also make a high-to-low transition which is referred to as "term line degradation."
This coupling is created by the gate oxide capacitance of the programming FETs B1, B2, . . . in the OR plane which are turned on. The amount of degradation depends upon the ratio of the gate oxide capacitance to the total term line capacitance. If a number of outputs are programmed for a particular term, the ratio may be quite significant. A consequence of such unwanted gate oxide capacitance is the degradation of the term line to a low enough level causing slow discharge of the output lines B and thus slows the evaluation of the OR plane.
One known technique used to overcome the problem of capacitive coupling is the addition of a buffer 9 (shown in phantom in FIG. 1) consisting of two series-connected inverters for each term line interconnected between the output of the AND plane and the input of the OR plane. This arrangement suffers from the drawbacks of requiring four FETs for each term line which increases use of chip area and thus increases manufacturing costs.
In addition, further details of other known programmable logic array devices were uncovered in a state of the art search directed to the subject matter of this application. The following U.S. Pat, Nos. were developed:
______________________________________ 4,041,458 4,728,827 4,516.040 4,740.721 4,516,123 4,745,307 4,546,273 4,760,290 4,661,728 4,783,606 ______________________________________
In U.S. Pat. No. 4,661,728 issued to M. Kashimura on Apr. 28, 1987, there is disclosed in FIG. 3 a programmable logic array which includes a product term (AND) array 1 and a sum term (OR) array 2. The product term array 1 is formed of a plurality of N-channel transistors connected in series to each of the term lines. The product term array 1 is coupled to a sampling circuit 3. The sum term array 2 is formed of a plurality of N-channel transistors connected in parallel to each of the corresponding input ends thereof. The product term output terminals P.sub.1 to P.sub.m are connected to gate electrodes of P-channel control transistors 10.sub.1 to 10.sub.m, respectively. The source electrodes of the control transistors are coupled to a power source VDD. and the drain electrodes thereof are coupled to respective input lines 20.sub.1 to 20.sub.m of the sum term array 2.
The sum term lines 30.sub.1 to 30.sub.m are coupled to the power source VDD via P-channel precharge transistors 40.sub.1 to 40.sub.m. A plurality of P-channel precharge transistors 11.sub.1 to 11.sub.m are coupled to the respective product term output terminals P.sub.1 to P.sub.m. A circuit 4 formed of N-channel transistors is coupled to the sum term array 2. The circuit 4 is used to maintain the input lines 20.sub.1 to 20.sub.m of the sum term array 2 at a low level during the precharge cycle.
The present invention represents an improvement over the prior art illustrated in FIG. 1 of the drawings and the prior art of U.S. Pat. No. 4,661,728. None of the prior art discussed above disclose a dynamic programmable logic array circuit with no "virtual grounds" like that of the present invention. In particular, the dynamic programmable logic array circuit of the instant invention includes an AND logic plane, an inter-plane buffer, and an OR logic plane. The inter-plane buffer is formed of a plurality of N-channel inter-plane FETs. Each of the plurality of N-channel inter-plane FETs has its gate electrode connected to a respective one of product term lines, and its source electrode connected to a respective one of OR input lines. The drain electrodes of the inter-plane FETs are connected to receive an OR plane evaluation signal.